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- Path: EU.net!sun4nl!xs4all!usenet
- From: jtv@asd01-23.dial.xs4all.nl (Jeroen T. Vermeulen)
- Newsgroups: comp.sys.amiga.programmer,comp.sys.amiga.misc
- Subject: Re: AB3D II beats Quake....
- Date: Fri, 29 Mar 96 18:53:20
- Organization: Leiden University, Mathematics & Computer Science, The Netherlands
- Message-ID: <19960329.7B4B090.10D7A@asd08-13.dial.xs4all.nl>
- References: <74000105753944194756@BIRDLAND> <10017.6659T1424T209@mbox.vol.it> <4jbcno$7m9@soleil.uvsq.fr> <4jcsb2$8te@nadine.teleport.com>
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-
- In article <4jcsb2$8te@nadine.teleport.com> sschaem@teleport.com (Stephan Schaem) writes:
-
- > Actually the P6 can issue 3 instruction per cycle...
-
- More precisely, it can both issue and retire up to 3 *micro* instructions per
- cycle, and some x86 instructions translate into over 100 micro instructions.
-
- With "both issue and retire" I mean of course that in any cycle, three micro
- instructions which have been issued in an earlier cycle can be completed and
- three new micro instructions can be started.
-
-
- > : On CISC, it's not possible, because opcode are not 32 bit aligned. This means
- > : that before decoding intstruction i, you must decode instructions 0 to i-1.
- >
- > Thats not a problem really... x86 nowdays have a risc core and decode the
- > x86 'language'. I heard that maybe 18% of the P6 is actually x86 related
- > the rest is just risc design.
-
- That doesn't really solve the "misaligned fetch" problem. But Intel was
- apparently incredibly lucky in discovering that the length of an instruction
- (and therefore the next fetch address) can be determined very quickly.
-
-
- > Stephan
-
- --
- ============================================================================
- # Jeroen T. Vermeulen \"How are we doing kid?"/ Yes, we use Amigas. #
- #--- jtv@xs4all.nl ---\"Oh, same as always."/-- ... --#
- #jvermeul@wi.leidenuniv.nl \ "That bad, huh?" / Got a problem with that? #
- I'll say one thing for Amsterdam: We have a lot of foreigners
-